首页> 外国专利> PARALLEL PROCESSING REED-SOLOMON ENCODING CIRCUIT AND PARALLEL PROCESSING REED-SOLOMON ENCODING METHOD USED FOR SAME

PARALLEL PROCESSING REED-SOLOMON ENCODING CIRCUIT AND PARALLEL PROCESSING REED-SOLOMON ENCODING METHOD USED FOR SAME

机译:并行处理里德-所罗门编码电路和并行处理里德-所罗门编码方法

摘要

PROBLEM TO BE SOLVED: To provide a parallel processing Reed-Solomon encoding circuit which can use an optimum number of parallel processes for a system by making it possible to use an arbitrary number of parallel processes.;SOLUTION: Multipliers corresponding to 1st inputs of 1st to 4th Galois field product sum circuits 134 are coefficients of 0-to 3rd order of a generating polynomial G(x). Multipliers corresponding to 2nd inputs of the 1st to 4th Galois field product sum circuits 131 to 134 are coefficients of 0-to 3rd order of a polynomial of the residue obtained by dividing x5 by the generating polynomial G(x). Multipliers corresponding to 3rd inputs of the 1st to 4th Galois field product sum circuits 131 to 134 are coefficients of 0-to 3rd order of a polynomial of the residue obtained by dividing x6 by the generating polynomial G(x). While an information signal is inputted from a 1st selector circuit 121 to a 3rd selector circuit 123, signals A, B, and C are outputted and when not, D, E, and F are outputted.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:提供一种并行处理的里德-所罗门编码电路,通过使用任意数量的并行处理,它可以为系统使用最佳数量的并行处理。解决方案:与第一输入的第一输入对应的乘法器第4〜第4Galois场积和电路134是生成多项式G(x)的0〜3阶的系数。对应于第一至第四伽罗瓦场积和电路131至134的第二输入的乘数是通过将x5除以生成多项式G(x)而获得的残差多项式的0至3阶系数。对应于第一至第四伽罗瓦场乘积和电路131至134的第三输入的乘数是通过将x6除以生成多项式G(x)而获得的残差多项式的0至3阶系数。当信息信号从第一选择器电路121输入到第三选择器电路123时,输出信号A,B和C,否则输出D,E和F.COPYRIGHT:(C)2001,JPO

著录项

  • 公开/公告号JP2001244821A

    专利类型

  • 公开/公告日2001-09-07

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP20000055250

  • 发明设计人 SEKI KATSUTOSHI;

    申请日2000-03-01

  • 分类号H03M13/15;

  • 国家 JP

  • 入库时间 2022-08-22 01:27:30

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