APPARATUS AND METHOD FOR SEPARATELY LAYERING CACHE AND ARCHITECTURAL SPECIFIC FUNCTIONS IN DIFFERENT OPERATIONAL CONTROLLERS TO FACILITATE DESIGN EXTENSION

摘要

A shared cache controller, comprising: a first bus interface unit (412) receiving operations for a storage unit within a storage hierarchy from a first processor; a second bus interface unit (414) receiving operations for the storage unit from a second processor; a plurality of controller units including: a cache controller unit (416) connected to the first and second bus interface units performing cache operations from the first and second processor for the storage unit; a first architectural controller unit (404) connected to the first bus interface unit performing at least a portion of architectural operations from the first processor for the storage unit; and a second architectural controller unit (406) connected to the second bus interface unit performing at least a portion of architectural operations from the second processor for the storage unit; and a throttle unit connected between the first and second processors and the storage unit, the throttle unit serializing a plurality of colliding cache operations from the first and second processors for the storage unit. 2187 כ" ה באלול התשס" א - September 13, 2001