A RECONFIGURABLE INTEGRATED CIRCUIT WITH INTEGRATED DEBUGGING FACILITIES FOR USE IN AN EMULATION SYSTEM

摘要

An integrated circuit is described as comprising a plurality of logic elemen ts (LEs), each of which having a plurality of outputs, and a partial scan register. The plurality of LEs are operative to generate a plurality of outp ut signals in response to a plurality of input signals correspondingly applied to the LEs. The partial scan register is reconfigurably coupled to select ones of the LEs such that, when enabled, the partial scan register is operative to capture and output on a scan bus a record of signal state values of circuit elements emulated by the selected LEs in a particular clock cycle of an operating clock, wherein the partial scan register is enabled with applicati on of a scan clock appropriately scaled to the operating clock.