MODIFIED REED-SOLOMON ERROR CORRECTION SYSTEM USING (w+i+1)-BIT REPRESENTATIONS OF SYMBOLS OF GF(2w+i )

摘要

An error correction system (10) includes a Reed-Solomon encoder (12) that encodes data in accordance with a distance d generator polynomial g (x) over GF to produce (w+i+1)-bit redundancy symbols. With a switch (14) in the closed position, the 11-bit data symbols are added to the contents of a register (18) in an adder (21). The sum is then multiplied in multipliers (15, 16 and 17) by constants which are the coefficients of the generator polynomial. The coefficients are in the form of their lowest weight 11-bit representations, and the multipliers (15-17) are implemented with a minimum number of exclusive-OR gates. The products from multipliers (15) and (16) are added, modulo 2, in adders (22) and (23) to the contents of registers (19) and (20), respectively. These sums then update the registers (18) and (19). Similarly, the product produced by the multiplier (17) updates the register (20).