首页> 外国专利> Digital/analog (D/A) converting device with unit current generating circuit having differential switching and reference voltage generating circuits

Digital/analog (D/A) converting device with unit current generating circuit having differential switching and reference voltage generating circuits

机译:具有具有差分开关和参考电压产生电路的单位电流产生电路的数字/模拟(D / A)转换装置

摘要

The D/A converting device disclosed includes a decoder (1), and a plurality of unit current generating circuits (2A-2G) each having a differential switching circuit (15) and a reference voltage generating circuit (18). The decoder (1) receives a digital input value of n bits and outputs a plurality of complementary pairs of digital signals corresponding to the n bits of the digital input value. Each unit current generating circuit (2A-2G) receives a complementary pair of digital signals from the decoder. The differential switching circuit (15) has two complementary current output terminals (8A,8B), a bias voltage input (10B) and a reference voltage input (11'). The two complementary current output terminals of the differential switching circuit are interconnected between corresponding ones of the unit current generating circuits with the interconnected points being made two complementary analog output terminals (4,5). Each of the analog output terminals and a power source terminal (6) are connected to a load circuit (RL), whereby analog output voltages corresponding to the digital signals inputted to digital input terminals (3A-3C) of the n bits are obtained at the analog output terminals. This enables the speeding up of a settling time by reducing overshoot and undershoot when the analog output full-swings.
机译:公开的D / A转换装置包括解码器(1)和多个单位电流产生电路(2A-2G),每个单位电流产生电路(2A-2G)具有差分开关电路(15)和参考电压产生电路(18)。解码器(1)接收n位的数字输入值,并输出与该n位数字输入值相对应的多个互补的数字信号对。每个单位电流产生电路(2A-2G)从解码器接收一对互补的数字信号。差分开关电路(15)具有两个互补电流输出端子(8A,8B),偏置电压输入(10B)和参考电压输入(11')。差分开关电路的两个互补电流输出端子互连在相应的单位电流产生电路之间,其中互连点为两个互补模拟输出端子(4,5)。模拟输出端子和电源端子(6)中的每一个都连接到负载电路(RL),由此获得与输入到n位的数字输入端子(3A-3C)的数字信号相对应的模拟输出电压。模拟输出端子。通过减少模拟输出全摆幅时的过冲和下冲,可以加快建立时间。

著录项

  • 公开/公告号EP0720300B1

    专利类型

  • 公开/公告日2001-10-17

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号EP19950120674

  • 发明设计人 TAKIGUCHI TOMIOC/O NEC CORP.;

    申请日1995-12-28

  • 分类号H03M1/74;

  • 国家 EP

  • 入库时间 2022-08-22 01:17:15

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