METHOD FOR MANUFACTURING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DUAL GATE ELECTRODE OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for manufacturing a complementary metal oxide semiconductor(CMOS) dual gate electrode of a semiconductor device is provided to prevent diffusion of dopants in a doped polysilicon layer, by additionally forming an insulating diffusion blocking layer between the doped polysilicon layer and a metal silicide layer. CONSTITUTION: An isolating layer(14) is formed on a semiconductor substrate(10). A p-well(11) and an n-well(12) adjacent to each other are formed in the substrate having the isolating layer. A gate insulating layer(16) is deposited on the entire surface of the substrate. An amorphous silicon layer is deposited on the gate insulating layer. N+ impurities are selectively implanted only into the amorphous silicon layer near the p-well portion while p+ impurities are implanted only into the amorphous silicon layer near the n-well portion. A cleaning process is performed regarding the resultant structure by using H2O2 and H2SO4, to form a diffusion blocking layer for preventing impurity diffusion on the amorphous silicon layer. A metal silicide layer is formed on the diffusion blocking layer. A rapid thermal process(RTP) is performed regarding the metal silicide layer. The stacked metal silicide layer, diffusion blocking layer and doped polysilicon layer(18a',18b') are patterned to form dual gate electrodes in the upper portions of the substrate of the p-well and n-well, respectively.