Data collision avoidance method in Half Duplex Direct Memory Access logic

摘要

PURPOSE: A method of preventing data collision in a half duplex direct memory access logic is provided which maintains a request-to-send signal at a high level for a predetermined period of time even after a transmission processor has transmitted data to a reception processor to control the initiation of a transmission direct memory access logic of the reception processor. CONSTITUTION: A transmission processor transmits a high request-to-send signal to an RTS/CTS controller. The RTS/CTS controller sets a clear-to-send signal of a reception processor to a low state. The transmission processor transmits data to the reception processor. When the reception of data has been completed, the reception processor initiates reception direct memory access logic. After completion of the data transmission, the transmission processor maintains the request-to-send signal at the high state until the reception direct memory access logic is finished.