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Flash memory with i - shaped potential unsaturated collar a gate and method for its production

机译:具有i形势不饱和环栅的闪存及其生产方法。

摘要

A novel flash memory has (a) a first conductivity type substrate (31) with spaced-apart second conductivity type source and drain regions (35, 36) at its surface; (b) T-shaped source and drain electrodes (35a, 36a) respectively formed on and in contact with the source and drain regions (35, 36); (c) an I-shaped floating gate (39) formed on the substrate between and in contact with the source and drain electrodes; and (d) a control gate (41) formed on the floating gate. Also claimed is a flash memory production process involving (i) forming first and second insulating layers (32) on a first conductivity type substrate (31); (ii) structuring the layers to produce two spaced-apart openings, through which second conductivity type impurities are implanted to form source and drain regions (35, 36); (iii) producing a second conductivity type semiconductor layer on the insulating layers and in the openings for contact with the source and drain regions; (iv) structuring the semiconductor layer to form T-shaped source and drain electrodes (35a, 36a) and then removing the second insulating layer; (v) applying a third insulating layer (38) over the entire surface, including the source and drain electrodes; (vi) applying and structuring a second conductivity type semiconductor layer to form an I-shaped floating gate (39) between and overlapping the source and drain electrodes (35a, 36a); (vii) producing a fourth insulating layer (40) on the entire surface, including the floating gate (39); and (viii) forming and structuring a semiconductor layer to produce a control gate (41) above the floating gate (39).
机译:一种新颖的闪存具有:(a)第一导电类型的基板(31),在其表面具有间隔开的第二导电类型的源极和漏极区域(35、36); (b)分别在源区和漏区(35、36)上形成并与其接触的T形源电极和漏电极(35a,36a); (c)在衬底上的源电极和漏电极之间并与之接触的I形浮栅(39); (d)形成在浮置栅极上的控制栅极(41)。还要求保护一种闪存制造工艺,该工艺包括:(i)在第一导电类型衬底(31)上形成第一和第二绝缘层(32); (ii)使层结构化以产生两个间隔开的开口,通过该开口注入第二导电类型的杂质以形成源极和漏极区(35、36); (iii)在绝缘层上和开口中产生第二导电型半导体层,以与源极和漏极区接触; (iv)构造半导体层以形成T形的源电极和漏电极(35a,36a),然后去除第二绝缘层; (v)在包括源极和漏极的整个表面上施加第三绝缘层(38); (vi)施加并构造第二导电类型的半导体层,以在源电极和漏电极(35a,36a)之间并与之重叠形成I形浮栅(39); (vii)在包括浮栅(39)的整个表面上产生第四绝缘层(40); (viii)形成并构造半导体层以在浮置栅极(39)上方产生控制栅极(41)。

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