Integrated semiconductor circuit includes a second dielectric layer which lies in the opening of a first dielectric layer and is planar to a first conducting layer

摘要

Integrated semiconductor circuit includes a second dielectric layer (D2) which lies in the opening of a first dielectric layer (D1) and is planar to a first conducting layer (M1). Integrated semiconductor circuit has a first conducting layer (M1), a first dielectric layer (D1) and a second conducting layer (M2) arranged on a semiconductor substrate. The first dielectric layer has an opening in the region of a capacitor surface (F). A second dielectric layer (D2) is arranged in the first dielectric layer and is thinner than the first layer. The second dielectric layer in the opening runs along the first conducting layer and planar to it. An Independent claim is also included for a process for the production of the integrated semiconductor circuit comprising: applying a first conducting layer (M1), a first dielectric layer (D1) and a second conducting layer (M2) onto a semiconductor substrate; removing the first dielectric layer in the region of a capacitor surface; and applying a second dielectric layer in the openings formed. The second dielectric layer is applied directly on the first layer in the region of the capacitor surface.