Frequency division of clock signal involves forming logical combination of first and second signals dependent on rising and falling clock signal edges and clock pulse counter states

摘要

The method involves resetting a clock signal clock pulse counter alternately after passing through two different count differences, forming a first signal whose logic state is altered by a rising clock edge if a defined first counter state exists, forming a second signal whose logic state is altered by a falling edge if a defined second counter state exists and producing a divided output clock signal with a logical combination of the two signals. The method involves resetting a clock counter counting a clock pulse of a clock signal alternately after passing through a first count difference and a second, different count difference, forming a first signal (rising Edge) whose logic state is altered by a rising clock signal edge if a defined first state of the first counter exists, forming a second signal (fallingEdge) whose logic state is altered by a falling signal edge if a defined second counter state exists and producing a divided output clock signal (clkDiv5) with a logical combination of the first and second signals. Independent claims are also included for the following: a frequency divider circuit.