Synchronous clock generating circuit for multiple sub-systems, in which synchronization signal is used as mechanism by which slave devices achieve identical and simultaneous phase alignments to internally generated clock in master device

摘要

The circuit for synchronizing multiple sub-systems uses one voltage-controlled oscillator. A phase and frequency aligned signal output from the voltage-controlled oscillator is transmitted to each sub-system within the digital system. The circuit for generating a synchronous clock generates a synchronization signal in a master device that is then supplied as an input to one or more slave devices. The synchronization signal provides a mechanism by which the slave devices achieve identical and simultaneous phase alignments to the internally generated clock in the master device. Independent claims are included for; a method for synchronizing multiple sub-systems using a single voltage-controlled oscillator.