首页> 外国专利> Semiconductor SRAM with reduced storage cell area and improved data retention interval has negative resistance section with tunnel insulating layer formed on active p-type region

Semiconductor SRAM with reduced storage cell area and improved data retention interval has negative resistance section with tunnel insulating layer formed on active p-type region

机译:具有减小的存储单元面积和改进的数据保留间隔的半导体SRAM具有负电阻部分,在有源p型区域上形成了隧道绝缘层

摘要

The negative resistance section (10a) includes a tunnel insulating layer (10t) producing the tunnel effect and is formed on the active p-type region (17a) with a relatively high concentration of lattice imperfections. In the tunnel insulation layer n-type polysilicon is formed. An Independent claim is included for the corresponding method of manufacture.
机译:负电阻部分(10a)包括产生隧道效应的隧道绝缘层(10t),并形成在有源p型区域(17a)上,具有较高的晶格缺陷浓度。在隧道绝缘层中,形成n型多晶硅。相应的制造方法包括独立权利要求。

著录项

  • 公开/公告号DE10020150A1

    专利类型

  • 公开/公告日2001-03-08

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI K.K. TOKIO/TOKYO;

    申请/专利号DE2000120150

  • 发明设计人 MORIMOTO RUI;

    申请日2000-04-25

  • 分类号G11C11/38;H01L27/108;

  • 国家 DE

  • 入库时间 2022-08-22 01:09:51

相似文献

  • 专利
  • 外文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号