Computer power optimization by speculative calling-up and clearing of data in a computer processor cache memory bank, in which orders can be carried out in an un-ordered fashion so reducing cache coherence latency

摘要

Device comprises a cache coherence test device assigned to the first of a number of processors, which is configured to generate a presence signal, a pre-clearing slot for use with the cache memory of the multiple processors and software for controlling the pre-clearance slot and the cache memory. An Independent claim is made for a method for minimizing cache coherence latency in a multi-processor system.