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Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis
Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis
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机译:利用数据屏蔽技术促进测试模式分析的集成电路存储设备
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摘要
Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.
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