Combined error position circuit and chien search circuit for reed- solomon decoding

摘要

A combined Chien search and error position circuit (116), for use in Reed-Solomon decoding, is disclosed. The circuit (116) operates in response to a zero signal (ZRO) issued by a root detection block (200) that iteratively evaluates an error locator polynomial &Lgr;(x) over the Galois field used in the coding. A zeroes register (218) and a position register (22) are provided, each of which have a plurality of stages (218. sub.0 through 218.sub.t ; 220.sub.0 through 220.sub.t). An index counter (208) maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block (200). An exponentiation circuit (212) performs a Galois field exponentiation of the count, and applies the result to the inputs of each of the zeroes register stages (218.sub.0 through 218.sub.t); the count is subtracted from the maximum Galois field index (e.g., from 255 for Galois field 256) and, for all but the zeroth iteration, the difference is applied to the inputs of each of the position register stages (220.sub.0 through 220.sub. t). A root counter (207) maintains a count of the number of roots identified by the root detection block (200), which is used to sequentially select the register stages (218.sub. 0 through 218.sub.t ; 220.sub.0 through 220.sub.t) into which the zeroes and position values are stored.