Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip

摘要

A wafer layout architecture and a method for producing multi- device PLDs wherein the wafer layout architecture includes device- linking conductors that allow a wafer to be diced into both single- device chips and multi-device chips. A multi-device chip is a single chip that includes two or more discrete PLD circuits that are connected by the device-linking conductors. Each device-linking conductor is formed on the wafer and extends across a scribe line space separating two discrete FPGA circuits. When the two discrete FPGA circuits are separated during a dicing process, the wafer is cut along the scribe line space and the device-linking conductor is severed. When a multi- device chip is formed that includes both of the discrete FPGA circuits, the device-linking conductor is selectively implemented using programmable switches to provide a signal path between the two discrete FPGA circuits. Because the device-linking conductors are formed on the chip, the device-linking conductors provide on-chip signal transmissions having substantially less delay than off-chip signal transmission methods.