Stabilization of single loop sigma-delta modulators of a high order

摘要

A sigma-delta modulator of second or higher order includes two or more integrating stages, and a comparator connected in cascade to the integration stages. A signal having a logic level +1 is generated when an input signal to the sigma-delta modulator is positive, and a signal having a logic value −1 is generated when the input signal is negative. Regardless of its absolute value, a feedback line includes a low-pass filter and an adder circuit for adding a feedback signal. The signal output by the last of the integrating stages is filtered by the low-pass filter. The sigma-delta modulator further includes a second comparator having an input connected in common to the input of the first comparator and an output connected to an input of the low-pass filter. The second comparator outputs a logic signal having a positive value when the input signal is positive, and outputs a logic signal having a negative value when the input signal is negative. The second comparator also outputs a signal having an increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value.