Template-based simulated annealing move-set that improves FPGA architectural feature utilization

摘要

A modification to the available simulated annealing algorithm is provided to better utilize direct connects and other architecture-specific features of a Field Programmable Gate Array. A preferred embodiment comprises adding a template-based move to the SA move-set that recognizes a specific pattern or template in the user's design after mapping, and arranges the components into the optimal configuration for the specific template discovered. The present invention increases the intelligence of the SA move-set by selectively supplementing the random moves in the move-set with moves that produce locally good solutions.