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Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
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机译:对缓存未命中和已完成指令的性能进行监控,以进行指令并行性分析
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摘要
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
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