Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency

摘要

A programmable device architecture that may improve functionality over look-up table based or product-term based programmable logic devices and that may provide for the efficient implementation of user-programmable logic designs resulting in implementations that may require less area and may provide increased performance. A product-term array (either fully or partially populated) may be placed in front of a number of LUT-based macrocells, utilizing the available routing wires as wordlines to form the product terms. The present invention takes advantage of existing routing to do more than just route signals from one point to another by allowing logic to be implemented in the same die area. The result is logic implementations that may require fewer total macrocells, fewer levels of macrocells, and fewer point-to-point nets (because logic density increases). The present invention may apply to FPGAs comprising an array of macrocells and to FPGAs comprising an array of clustered macrocells. The present invention may also be used with CPLDs by replacing the product term matrix, OR gates, and macrocells with LUT-based macrocells. The present invention may be used to implement logic functions in fewer macrocells than may be implemented in either LUT-based macrocells or product-term based macrocells alone.