Method for reducing critical dimension of dual damascene process using spin-on-glass process

摘要

A method for forming wiring structures in integrated circuit devices is disclosed. The method, in one embodiment, firstly providing a substrate is carried out. Then an interlayer dielectric layer is formed over the substrate. Sequentially an etching stop layer is formed and wherein the etching stop layer is patterned. Thus formation of a dielectric layer over the etching stop is achieved. Also photoresist mask is formed and defined. Therefore an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etching stop layer therein. Consequentially removing the photoresist mask and then depositing a first conductive metal layer are all carried out. Again, photoresist mask is formed and defined. The next step is removing excess parts of the conductive metal. Sequentially the step is depositing a second conductive metal layer. Finally the surface of integrated circuit device is planarized herein.