Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like

摘要

Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.