首页> 外国专利> Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line

Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line

机译:缓存,包括用于存储缓存行的预取方式,并配置为在访问预取的缓存行时将预取的缓存行移至非预取方式

摘要

A cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests initiated by a microprocessor connected to the cache are stored into the non-prefetch ways. Accessed cache lines are thereby maintained within the cache separately from prefetch cache lines. When a prefetch cache line is presented to the cache for storage, the prefetch cache line may displace another prefetch cache line but does not displace an accessed cache line. A cache hit in either the prefetch way or the non-prefetch ways causes the cache line to be delivered to the requesting microprocessor in a cache hit fashion. The cache is further configured to move prefetch cache lines from the prefetch way to the non-prefetch way if the prefetch cache lines are requested (i.e. they become accessed cache lines). Instruction cache lines may be moved immediately upon access, while data cache line accesses may be counted and a number of accesses greater than a predetermined threshold value may occur prior to moving the data cache line from the prefetch way to the non-prefetch way. Additionally, movement of an accessed cache line from the prefetch way to the non-prefetch way may be delayed until the accessed cache line is to be replaced by a prefetch cache line.
机译:高速缓存采用一种或多种预取方式来存储预取高速缓存行,以及一种或多种方式来存储所访问的高速缓存行。预取高速缓存行存储在预取方式中,而响应于由连接到该高速缓存的微处理器发起的请求的高速缓存未命中而取回的高速缓存线则存储在非预取方式中。从而将访问的缓存行与预取缓存行分开保存在缓存中。当将预取高速缓存行呈现给高速缓存进行存储时,预取高速缓存行可以替换另一个预取高速缓存行,但不替换访问的高速缓存行。以预取方式或非预取方式命中的高速缓存命中都会使高速缓存行以高速缓存命中的方式传递到发出请求的微处理器。高速缓存还被配置为:如果请求了预取高速缓存行(即,它们变为被访问的高速缓存行),则将预取高速缓存行从预取方式移动到非预取方式。指令高速缓存线可以在访问时立即移动,同时可以对数据高速缓存线访问进行计数,并且在将数据高速缓存线从预取方式移动到非预取方式之前,可能发生大于预定阈值的访问次数。另外,被访问的高速缓存行从预取方式到非预取方式的移动可以被延迟,直到访问的高速缓存行将被预取高速缓存行代替为止。

著录项

  • 公开/公告号US6219760B1

    专利类型

  • 公开/公告日2001-04-17

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US20000558891

  • 发明设计人 BRIAN D. MCMINN;

    申请日2000-04-26

  • 分类号G06F120/00;G06F130/00;

  • 国家 US

  • 入库时间 2022-08-22 01:04:33

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