Method for Quad-word Storing into 2-way interleaved L1 cache

摘要

A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.