Optimizing cache data load required for functions in loop routine by sequentially collecting data in external memory for single block fetch

摘要

The performance of a computer architecture having cache memory is optimized by reorganizing the structure of information before such information is written into an external memory coupled to a processor. Specifically, loops of repeated processing steps are identified, each loop routine operating upon particular data and in response to particular instructions. The instructions and data for these loop routines are organized into structures of information, each of which comprises all instructions or data for one loop routine. Each structure is stored into external memory and can be brought into cache memory as a single block of information.