Data processing circuit with cache memory - has first and second command transfer memories for single and multiple line commands, and transfers required commands to cache memory

摘要

The data processing circuit includes a cache memory (20) for storing commands, and a command processor (21) for instructing a storage device (22) of lower order w.r.t. the command cache memory. The instruction transfers a required command to the cache memory when the required command is not yet in the memory. The processing circuit includes a command transfer data memory (23) for storing single line command data. A second command transfer data memory (24) consisting of one or more stages stores one or more lines of command data which are transferred after the single-line command data. Called up commands are carried out at higher speeds. ADVANTAGE - With computer system, CPU. High capacity. Fast transfer of commands.