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Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
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机译:通过指令重试在精简指令集计算机处理器中进行瞬时错误恢复的系统和方法
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摘要
Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.
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