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Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory

机译:利用单隧道氧化物的nand阵列闪存双源极多晶硅选择栅结构和编程方法

摘要

A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
机译:串联选择晶体管和源极选择晶体管串联连接在浮栅数据存储晶体管的NAND串的末端。浮置栅极,串联选择栅极和源极选择栅极均优选地由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮栅数据存储晶体管的栅极氧化物。串联选择栅和源极选择栅中的两层多晶硅连接在一起。串联选择晶体管与NAND串中的最后一个晶体管相连。源极选择晶体管与阵列Vss电源相连。为了在另一个NAND单元的编程期间编程禁止特定的NAND单元,将串联选择晶体管的栅极升高到Vcc,同时将源选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受更高的电压,而不会在串联或源极选择晶体管中引起栅二极管结或氧化物击穿。

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