JTAG boundary scan cell with enhanced testability feature

摘要

A boundary scan cell for testing an integrated circuit comprises an output buffer for driving a pad of the integrated circuit, a capture register coupled to the pad through the output buffer, and an input buffer drives a signal present at the pad to a node coupled to core logic of the IC. A first multiplexer is included to have a first input coupled to the node, a second input coupled to data of a previous scan stage, and an output coupled to the capture register. Logic circuitry selectively enables/disables the input and output buffers responsive to first and second control signals such that the I/O buffers can drive the pad and, at the same time, drive the input buffer, the output of which is coupled to the input of the capture register.