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Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array
Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array
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机译:具有一组关联缓存的计算机系统,该缓存具有顺序访问的片上地址标签阵列和片外数据阵列
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摘要
A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.
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