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Symbol based algorithm for hardware implementation of cyclic redundancy check
Symbol based algorithm for hardware implementation of cyclic redundancy check
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机译:基于符号的循环冗余校验硬件实现算法
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摘要
A method and apparatus for generation of CRC generation/checker circuitry. A symbolic simulation-based algorithm to derive boolean equations for a parameterizable data-width CRC generator/checker is described. The equations generated are used to implement a data-flow representation of the CRC circuit in VHDL. The VHDL description is then synthesized into gates.
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