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Pipeline processing apparatus for reducing delays in the performance of processing operations
Pipeline processing apparatus for reducing delays in the performance of processing operations
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机译:用于减少处理操作的执行延迟的管道处理设备
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摘要
A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.
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