Double amplitude of integrated circuit tip/chip and AGP/DDR interface for decrease amplitude (SSTL) signal

摘要

(57) Abstract I/O interface, has latch, the clock, and the adjustment circuit which are mounted on private physical layout, plural protocol and reliability to the high frequency bus which executes signal specification to be high and offer the interface which has pliability. Before transmitting to the pad and the core, three clock trees are used the input/output signal for the buffering of these signals and in order to synchronize adjustment. Three kurotsukutsuri are mounted by the layout of exclusive use, make the strict control of clock/strobe parameter (for example, the skew and duty cycle, to stand up,/to go down, time) possible. Two clock trees section are arranged in I/O interface, the trigger do the plural output latches which are formed while executing in order the buffering to do the output data signal from the core with asynchronous or synchronous mode. With synchronous mode, in regard to the data, that to do the edge center or either of the window Woo strobe it is possible the clock/the strobe. The 3rd clock tree transmits the clock/the strobe from the external source, in order the buffering to do the input data from the pad with window - strobe mode or edge central mode, is used the plural input latches which are formed while executing for in order the trigger to do. As for I/O interface, in addition, in order AGP/DDR protocol, and, to conform to double amplitude, decrease amplitude (SSTL), and TTL signal specification, the adjustment circuit which adjusts the I/O signal is had.