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Addition/relative/selecting circuit, maximum likelihood sequence detector, and addition/relative/function preselection capability run manner

机译:加法/相对/选择电路,最大似然序列检测器以及加法/相对/功能预选能力的运行方式

摘要

A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.
机译:采用维特比算法的检测器系统包括一种装置和方法,该装置和方法构造了双态网格结构,用于相对于观察到的信道输出样本序列确定最可能的接收符号序列。在双重状态格架中,识别出具有等效分支度量值的状态对,它们在路径选择期间也具有相同的决策,因此允许这些状态对共享先前状态度量的比较操作。因此,为了计算更新的或当前的状态度量值,加,比较和选择(ACS)电路可以仅比较先前的状态度量值以确定两个状态之间的转换的最小值,同时将每个先前的状态度量值与其值相结合。相应的分支度量以提供更新的或当前状态度量值。

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