首页> 外国专利> METHOD FOR FORMING TRANSISTOR GATE DIELECTRIC HAVING HIGH DIELECTRIC CONSTANT REGION AND LOW DIELECTRIC CONSTANT REGION

METHOD FOR FORMING TRANSISTOR GATE DIELECTRIC HAVING HIGH DIELECTRIC CONSTANT REGION AND LOW DIELECTRIC CONSTANT REGION

机译:具有高介电常数区和低介电常数区的晶体管栅极介电层的形成方法

摘要

PROBLEM TO BE SOLVED: To provide a method for forming a transistor gate dielectric, having the combination of a high dielectric constant region and a low dielectric constant region.;SOLUTION: The method for forming the transistor gate dielectric is provided with a process (a) for forming a dummy layer over a semiconductor structure, patterning the dummy layer and forming a gate opening; turning the bottom part of the gate opening to the upper surface of the semiconductor structure at the time; a process (b) of forming the dielectric layer of the high dielectric constant on the bottom part and sidewall of the dummy dielectric layer and forming the dielectric layer of the low dielectric constant on the dielectric layer of the high dielectric constant; a process (c) of forming a spacer on the sidewall of the gate opening; a process (d) of etching the dielectric layer of the low dielectric constant at a part which is not covered with the spacer; a process (e) of removing the spacer and the process (f) of forming a gate electrode on the dielectric layer of the high dielectric constant and the dielectric layer of the low dielectric constant in the gate opening.;COPYRIGHT: (C)2002,JPO
机译:要解决的问题:提供一种形成晶体管栅极电介质的方法,该方法具有高介电常数区域和低介电常数区域的组合;解决方案:提供了一种形成晶体管栅极电介质的方法( )用于在半导体结构上形成伪层,构图伪层并形成栅极开口;此时,将栅极开口的底部转向半导体结构的上表面;步骤(b),在虚拟介电层的底部和侧壁上形成高介电常数的介电层,并在高介电常数的介电层上形成低介电常数的介电层; (c)在栅极开口的侧壁上形成隔离物的工序; (d)在未被隔离物覆盖的部分上蚀刻低介电常数的电介质层的工序(d)。工序(e)的去除工序和工序(f)在栅极开口中的高介电常数的介电层和低介电常数的介电层上形成栅电极的步骤。版权所有(C)2002 ,日本特许厅

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