GATED CLOCK DESIGN SUPPORT SYSTEM, GATED CLOCK DESIGN SUPPORT METHOD AND GATED CLOCK DESIGN SUPPORT PROGRAM

摘要

PROBLEM TO BE SOLVED: To set a timing restriction which reflects delay time from a gated buffer to a register accurately with respect to enable logic.;SOLUTION: A gated clock design is one of design methods for reducing power consumption of a logic circuit. In order to operate a gated clock designed logic circuit correctly as specified, a timing restriction imposed to an enable logic for controlling clock signal supply must be satisfied. This timing restriction must also take the delay time of clock signal into account. When design is supported to satisfy the timing restriction imposed to the enable logic while take account of the delay time of clock signal, timing restriction which reflects the delay time from a gated buffer to a register accurately can be set with respect to the enable logic.;COPYRIGHT: (C)2002,JPO