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ACCUMULATING ADDITION-SUBTRACTION CIRCUIT FOR ABSOLUTE VALUE

机译:累积绝对值的加减运算电路

摘要

PROBLEM TO BE SOLVED: To provide an accumulating addition-subtraction circuit for the absolute value capable of executing accumulating addition-subtraction for the absolute value at a high speed on a small scale circuit.;SOLUTION: The accumulating addition-subtraction circuit for the absolute value is provided with an adder-subtracter performing addition-subtraction of two data that are expressed by a complement of 2, a control unit of an adder-subtracter generating a control signal that controls selection whether aforementioned two data are to be added or subtracted and outputting to the adder-subtracter, and a register housing calculated result of the adder-subtracter and also supplying to the adder-subtracter.;COPYRIGHT: (C)2002,JPO
机译:要解决的问题:提供一种用于绝对值的累加减法电路,该电路能够在小规模电路上高速执行对绝对值的累加减法;解决方案:用于绝对值的累加减法电路该值被提供给执行由2的补码表示的两个数据的加减法的加减法器,加法减法器的控制单元生成控制信号的控制信号,该控制信号控制选择是否要对上述两个数据进行相加或相减。输出到加法器和减法器,并在寄存器中存储加法器和减法器的计算结果,并提供给加法器。;版权:(C)2002,JPO

著录项

  • 公开/公告号JP2002132494A

    专利类型

  • 公开/公告日2002-05-10

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC WORKS LTD;

    申请/专利号JP20000327715

  • 发明设计人 SHOJI TAKEMASA;MASUDA KOICHI;

    申请日2000-10-26

  • 分类号G06F7/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:54:14

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