--> addition result. A first delay circuit delays the second addition result by a predetermined delay to produce the delayed addition result while outputting the delayed addition result as the operation result.;This arithmetic circuit is simple in construction and is operable at a high speed and with a minimum of power consumption."/> Arithmetic circuit for calculating and accumulating absolute values of the difference between two numerical values
首页> 外国专利> Arithmetic circuit for calculating and accumulating absolute values of the difference between two numerical values

Arithmetic circuit for calculating and accumulating absolute values of the difference between two numerical values

机译:用于计算和累积两个数值之间的差的绝对值的算术电路

摘要

Described is an arithmetic circuit for calculating and accumulating absolute values of a difference between a first and a second numerical value having a predetermined bit length and represented by 2's complement notation and outputting an accumulation result as an operation result. Said circuit comprises a first inverter for inverting the second numerical value to produce an inverted value. A first adder produces a sum of the first numerical value and inverted value and outputs the sum as a first addition result. A second inverter inverts the first addition result to output an inverted addition result. A selector selects either one of the inverted addition result and first addition result on the basis of the sign of the first addition result and outputs the one result as a selected value. A correcting value generating circuit outputs a correcting value on the basis of the sign of the first addition result. A second adder produces a sum of the selected value, the correcting value and a delayed addition result and outputs the sum as a second addition result. A first delay circuit delays the second addition result by a predetermined delay to produce the delayed addition result while outputting the delayed addition result as the operation result.;This arithmetic circuit is simple in construction and is operable at a high speed and with a minimum of power consumption.
机译:描述了一种算术电路,该算术电路用于计算和累积具有预定位长并且由2的补码表示的第一数值和第二数值之间的差的绝对值,并输出累积结果作为运算结果。所述电路包括第一反相器,用于将第二数值反相以产生反相值。第一加法器产生第一数值和倒数值的和,并输出该和作为第一加法结果。第二反相器将第一加法结果反相以输出反相的加法结果。选择器基于第一相加结果的符号来选择反转相加结果和第一相加结果中的一个,并且将一个结果输出为选择值。校正值产生电路基于第一相加结果的符号输出校正值。第二加法器产生所选值,校正值和延迟的加法结果之和,并将该和作为第二<!-EPO ->加法结果输出。第一延迟电路将第二加法结果延迟预定的延迟,以产生延迟的相加结果,同时输出延迟的相加结果作为运算结果。该算术电路结构简单,可高速运行且最小化。能量消耗。

著录项

  • 公开/公告号EP0424838A2

    专利类型

  • 公开/公告日1991-05-02

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP19900120197

  • 发明设计人 KANOH TOSHIYUKIC/O NEC CORPORATION;

    申请日1990-10-22

  • 分类号G06F7/544;

  • 国家 EP

  • 入库时间 2022-08-22 05:52:54

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号