--> addition result. A first delay circuit delays the second addition result by a predetermined delay to produce the delayed addition result while outputting the delayed addition result as the operation result.;This arithmetic circuit is simple in construction and is operable at a high speed and with a minimum of power consumption."/>
公开/公告号EP0424838A2
专利类型
公开/公告日1991-05-02
原文格式PDF
申请/专利权人 NEC CORPORATION;
申请/专利号EP19900120197
申请日1990-10-22
分类号G06F7/544;
国家 EP
入库时间 2022-08-22 05:52:54