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Method for polysilicon conductor (PC) Trimming for shrinking critical dimension and isolated-nested offset correction
Method for polysilicon conductor (PC) Trimming for shrinking critical dimension and isolated-nested offset correction
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机译:缩小临界尺寸和隔离嵌套校正的多晶硅导体修剪方法
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摘要
A method of forming a semiconductor device, includes providing a structure having a first critical dimension, forming a lithographic pattern on the structure, and etching the structure with an O2-containing material to trim the first critical dimension to a second critical dimension, the second critical dimension being smaller than the first critical dimension. Thereafter, any offset between the nested features and the isolated feature can be corrected.
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