Ground bounce reduction technique using phased outputs and package de-skewing for synchronous buses

摘要

A technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses is described. In one embodiment, the output buffers of an integrated circuit (“IC”) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This deskewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.