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Fast 16-B early termination implementation for 32-B multiply-accumulate unit
Fast 16-B early termination implementation for 32-B multiply-accumulate unit
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机译:32-B乘法累加单元的快速16-B提前终止实现
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摘要
An embodiment of the present invention is a mixed length encoding unit. The mixed length may be a 12/16 bits (12/16-b) encoding algorithm within a multiply-accumulate (MAC). The mixed length encoding unit includes 16-b Booth encoder adapted to produce eight partial product vectors from sixteen bits of data. The 16-b Booth encoder is coupled to a four stage Wallace Tree. During a first cycle of the invention, a multiplex system directs the eight partial products and an accumulation vector to a four stage Wallace Tree. During subsequent cycles, the multiplex system directs six partial product vectors, an accumulation vector, one carry-feedback input vector, and one sum-feedback input vector to the four stage Wallace Tree.
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