Internal clock signal generator including circuit for accurately synchronizing internal clock signal with external clock signal

摘要

An internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) or phase locked loop (PLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.