Method for evaluating soft error immunity of CMOS circuits

摘要

A method for evaluating the robustness of a logic circuit to soft errors involves injecting a current pulse into a node of the logic circuit. The current pulse is shaped to be representative of a high-energy particle strike, and may have an amplitude that is sufficient to momentarily discharge an output node of the logic circuit. The output node of the logic circuit is electrically monitored to determine whether a transition occurs from a first logic state to a second logic state in response to the injected current pulse. In the case where the state of the output node does flip in response to the injected current pulse, a waveform of the injected current pulse is integrated over time to compute a critical charge level (Q_CRIT). Where the amplitude is insufficient to cause the output node to flip, the amplitude of the injected current pulse is incremented and the above steps are repeated using the incremented amplitude until a logic state transition does occur at the output node.