Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write

摘要

A messaging scheme that conserves system memory bandwidth and maintains cache coherency during a victim block write operation in a multiprocessing computer system is described. A source node having a dirty victim cache block—a modified cache block that is being written back to a corresponding system memory—sends a victim block command along with the dirty cache block data to the target processing node having associated therewith the corresponding system memory. The target node responds with a target done message sent to the source node and also initiates a memory write cycle to transfer the received cache block to the corresponding memory location. If the source node encounters an invalidating probe between the time it sent the victim block command and the time it received the target done response, the source node sends a memory cancel response to the target node. The memory cancel response helps maintain cache coherency within the system by causing the target node to abort further processing of the memory write cycle involving the victim block because the victim block may no longer contain the valid data. The memory cancel response may also conserve the system memory bandwidth by attempting to avoid relatively lengthy memory write cycles when the victim block may represent stale data. If the source node receives the target done response and if the victim block is still valid, the source node sends, instead, a source done message to the target node to indicate completion of the victim block transfer operation and to allow the target node to commit the victim block to the corresponding memory location.