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Power MOSFET having laterally three-layered structure formed among element isolation regions
Power MOSFET having laterally three-layered structure formed among element isolation regions
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机译:在元件隔离区域之间形成具有横向三层结构的功率MOSFET
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摘要
A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.
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