Low column leakage nor flash array-double cell implementation

摘要

The present invention relates to a flash memory array architecture, comprising a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith. The plurality of memory cells are configured as sets of two series-connected memory cells, wherein two sets of such memory cells are coupled together in parallel between a respective bit line and an individually selectable source line. In addition, the flash memory array architecture comprises a plurality of word lines, wherein each of the plurality of memory cells associated with one of the plurality of bits lines is coupled to a respective one of the plurality of word lines. The present invention further comprises a method of reading flash memory cells associated with such an architecture.