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Way to compensate the effect of coupling between bitlines in a multi-port memories
Way to compensate the effect of coupling between bitlines in a multi-port memories
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机译:补偿多端口存储器中位线之间耦合效应的方法
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摘要
The present invention is directed to a system and method of compensating for coupling capacitance between bit lines in multi-port memories. The complementary bit lines are switched between a core cell and a modified core cell. The modified core cell may invert the connections to the access transistors. This results in the writing of data into the cell correctly while compensating for coupling capacitance.
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