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Phase locked loops including analog multiplier networks that can provide constant loop bandwidth

机译:锁相环,包括可提供恒定环路带宽的模拟乘法器网络

摘要

Phase locked loops include an analog multiplier network, wherein the loop filter and the analog multiplier network are serially connected between the phase detector and the controlled oscillator of the phase locked loop. The analog multiplier network does not require an external network or digital signals from a digital bus. The analog multiplier network can provide an analog linearizer that equalizes the loop bandwidth of the phase locked loop as a function of frequency. More specifically, the analog multiplier network equalizes the loop bandwidth of the phase locked loop as a function of frequency, to provide constant loop bandwidth for the phase locked loop as a function of frequency.
机译:锁相环包括模拟乘法器网络,其中,环路滤波器和模拟乘法器网络串联连接在锁相环的鉴相器和受控振荡器之间。模拟乘法器网络不需要外部网络或来自数字总线的数字信号。模拟乘法器网络可以提供一个模拟线性化器,该线性化器使锁相环的环路带宽等于频率的函数。更具体地说,模拟乘法器网络根据频率来均衡锁相环的环路带宽,以根据频率为锁相环提供恒定的环路带宽。

著录项

  • 公开/公告号US6353348B1

    专利类型

  • 公开/公告日2002-03-05

    原文格式PDF

  • 申请/专利权人 ERICSSON INC.;

    申请/专利号US20000671423

  • 发明设计人 ROBERT J. BLASER;

    申请日2000-09-27

  • 分类号H03L70/60;

  • 国家 US

  • 入库时间 2022-08-22 00:46:39

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