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Digital to analog converter employing sigma-delta loop and feedback dac model

机译:采用sigma-delta环路和反馈dac模型的数模转换器

摘要

A circuit topology and method for converting a digital input signal to an analog output signal employs a modified sigma-delta loop and a DAC, and operates with improved accuracy over a wide frequency range. A loop filter such as a digital accumulator receives an input signal proportional to the difference between a digital input signal and a feedback signal. A quantizer quantizes the output of the loop filter, and the DAC converts the quantized signal into an analog output signal. The quantized signal is also provided to a DAC model. In response to the quantized signal and behavioral information about the DAC, the DAC model varies the feedback signal to match expected output signals from the DAC, including errors introduced by the DAC. By the operation of the sigma-delta loop, the errors of the DAC are substantially reduced.
机译:用于将数字输入信号转换为模拟输出信号的电路拓扑和方法采用改进的sigma-delta环路和DAC,并在较宽的频率范围内以提高的精度工作。诸如数字累加器的环路滤波器接收与数字输入信号和反馈信号之间的差成比例的输入信号。量化器对环路滤波器的输出进行量化,DAC将量化后的信号转换为模拟输出信号。量化信号也提供给DAC模型。响应于有关DAC的量化信号和行为信息,DAC模型改变反馈信号以匹配来自DAC的预期输出信号,包括DAC引入的误差。通过sigma-delta环路的操作,DAC的误差大大降低了。

著录项

  • 公开/公告号AU9631601A

    专利类型

  • 公开/公告日2002-04-08

    原文格式PDF

  • 申请/专利权人 TERADYNE INC.;

    申请/专利号AU20010096316

  • 发明设计人 TIMOTHY W. SHEEN;

    申请日2001-09-26

  • 分类号H03M3/04;

  • 国家 AU

  • 入库时间 2022-08-22 00:38:47

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