Method for testing an integrated circuit with flexible control of the clock

摘要

Circuit has core and memory cells with inputs and outputs alternately connected to the core inputs and outputs. The core has a clock input which receives a first clock signal in normal operation. Each memory cell is identified by an address and receives a second clock signal in test mode, with the core clock input blocked in test mode. The method has the following steps: configuration of test mode circuit, selection of a memory cell virtual address and lifting of core clock blocking for a limited period after the selection. An Independent claim is made for an integrated circuit with a central core and associated memory cells arranged to allow testing. Core clock inhibition control is by use of JTAG conforming instruction chains.